Wireless communication has extensive applications in consumer and business markets. Among the many communication applications are: fixed wireless, unlicensed (FCC) wireless, local area network (LAN), cordless telephony, personal base station, telemetry, mobile wireless, and other digital data processing applications. While each of these applications utilizes spread spectrum communications, sometimes they utilize unique incompatible communication protocols, e.g., using incompatible code sequences. Consequently, each application may utilize a unique hardware, software, and methodology for generating code sequences. This practice can be costly in terms of design, testing, manufacturing, and infrastructure resources. As a result, a need arises to overcome the limitations associated with the varied hardware, software, and methodology of providing code sequences in each of the varied wireless applications.
Within the wireless cellular telephony applications, both time division multiple access (TDMA) and code division multiple access (CDMA) are popular. While a CDMA system depends heavily upon code generation functions in both the transmitter and the receiver, a TDMA system also depends upon code generation. One of the code sequences used in wireless communications is a pseudonoise (PN) sequence, so named because of its deterministic, yet noise-like characteristics. Users, or channels, are offset in phase from each other within the same PN sequence, or code space, to provide them with a unique identity. Consequently, in order to detect a user's standard PN sequence within a received signal, a need arises for a method and apparatus to advance within the code space by desired code offsets.
One popular method of generating a PN sequence is to use a Galois LFSR, also known as a multiple sequence shift register (MSSR). Unfortunately, there is no practical method of calculating a mask by which the Galois field can be advanced. A mask is a circuit utilizing a mask word of bits that selectively enables the states of an LFSR to be combined. The states that are combined result in an output from the mask that is offset in code space from the LFSR's location in code space, e.g., provides a code sequence out of the mask that is phase shifted 32 chips from the LFSR's code sequence. Prior art FIG. 1C provides an example of a mask circuit. Instead, a Galois LFSR can be advanced by recording a block of multiple code sequences in memory, wherein each sequence has a different phase offset. For example, if a PN code sequence has a length of 215, and if a thirty-bit length of the PN sequence is desired, then approximately 15 kilobits of memory is required to store all the thirty-bit lengths located at 64 chip offsets from each other throughout the entire code space. However, memory is expensive and consumes both area and power in integrated circuit implementations. The performance of this alternative can be improved, at the cost of additional memory, by recording a finer resolution of offsets, e.g., every 16th offset in code space. However, even with finer resolutions, if a desired code offset does not match a stored code offset, then the LFSR may have to be extensively slewed. That is, the LFSR can be sped up, or slowed down (slewed), to change its phase with respect to the incoming data stream, thereby effectively advancing or retarding the relative phase offset between the two codes. However, even this method consumes computation time and power. In view of these shortcomings, a need arises to overcome the limitations of time, accuracy, and resource-inefficiency in advancing a Galois LFSR through code space.
Referring now to prior art FIG. 1A, a block diagram of a conventional Fibonacci linear feedback shift register (F-LFSR) 100 is shown. F-LFSR 100 has a well-known construction and operation, which includes multiple memory registers each holding a state. A least significant bit (LSB) 102 is provided on the right side of F-LFSR 100, a most significant bit (MSB) 106 is provided on the left side, and an intermediate bit (IB) 104 is provided in between. The Fibonacci feedback configuration sums a state of the MSB 106 with a state from an appropriate tap, e.g., from LSB 102 for this particular configuration, via adder 108. The sum is then input as the state for LFB 102. Each time a cycle occurs, this process is repeated with the new state values in the memories of each bit. The PN sequence generated by F-LRSR 100 is received at tap location 111 in this particular configuration.
Referring now to prior art FIG. 1B, a block diagram of a conventional Galois linear feedback shift register (G-LFSR) 150 is shown. The G-LFSR has an LSB 152, an IB 154, and an MSB 156, with an inter-bit adder 158 located only between MSB 156 and the next lowest bit, e.g., IB 154. G-LFSR 150 has an output tap 161 for receiving the PN sequence in this particular configuration. G-LFSR 150 is capable of generating a mask for a Fibonacci LFSR using known methods that advance the Fibonacci LFSR through code space. However, it is not known how to use an LFSR to generate a mask for a F-LFSR. Consequently, a need arises for a method and apparatus that can generate a mask for a Galois LFSR to provide advancements through code space.
Referring now to prior art FIG. 1C, a conventional mask circuit 170 is shown. Mask circuit 170 has multiple memory registers referred to as mask registers, e.g., mask register 1171a through mask register M 171m. The number of mask registers, M, usually matches the number of memory registers in an LFSR to which it is coupled. Thus, for example, mask circuit 170 would have M=N registers if it were coupled to F-LFSR 100 of prior art FIG. 1A. The value ‘m’ also refers to he number of AND gates, e.g., 172a-172m, and outputs 174a-174m coupled thereto. Inputs 110 through 113 correspond to the outputs from F-LFSR in prior art FIG. 1A. An adder 176a is provided at each gate output, except for the highest order gate 172m, wherein the results are summed from more significant bits. A final output line 178 provides the sum of the outputs from all the AND gates, 172a-172m. Mask registers 1171a through M 171m, receive a bit of a mask word, e.g., from memory, that enables a respective AND gate. The specific mask word, and the output provided on line 178, correspond to a predetermined advance in code space. As mentioned, a mask circuit with a mask word similar to mask 170 can be applied to a F-LFSR 100 in FIG. 1A. However, there is no known method to determine a mask word for a mask circuit coupled to a G-LFSR, e.g., G-LFSR 150 of FIG. 1B. Additional detail on LFSRs, fields, and mask circuits is provided in Chapter 6 of “CMDA Systems Engineering Handbook”, by Jhong Sam Lee and Leonard E. Miller. This reference is hereby incorporated by reference.
In another scenario, a communication protocol or a communication device may require the use of multiple code generators. For example, a communication protocol may require the use of both a Galois LFSR and a Fibonacci LFSR. By requiring two code advancement techniques with no apparent commonality, both individual systems must be provided. This will increase hardware size, power requirements, and resource needs. Resultantly, a need arises to overcome the limitation of hardware proliferation needed for generating code offsets for multiple LFSR configurations.